 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PIC18F6393/6493/8393/8493 Data Sheet 64/80-Pin High Performance, Flash Microcontrollers with LCD Driver, 12-Bit ADC and nanoWatt Technology (c) 2007 Microchip Technology Inc. Preliminary DS39896A Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39896A-page ii Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 64/80-Pin High-Performance, Flash Microcontrollers with LCD Driver, 12-Bit ADC and nanoWatt Technology LCD Driver Module Features: * Direct Driving of LCD Panel * Up to 192 Pixels: Software Selectable * Programmable LCD Timing module: - Multiple LCD timing sources available - Up to four commons: Static, 1/2, 1/3 or 1/4 multiplex - Static, 1/2 or 1/3 bias configuration * Can Drive LCD Panel while in Sleep mode for Low-Power Operation Peripheral Highlights: * 12-Bit, Up to 12-Channel Analog-to-Digital (A/D) Converter module: - Auto-acquisition capability - Conversion available during Sleep * High-Current Sink/Source 25 mA/25 mA * Four External Interrupts * Four Input Change Interrupts * Four 8-Bit/16-Bit Timer/Counter modules * Real-Time Clock (RTC) Software module: - Configurable 24-hour clock, calendar, automatic 100-year or 12,800-year, day-of-week calculator - Uses Timer1 * Up to Two Capture/Compare/PWM (CCP) modules * Master Synchronous Serial Port (MSSP) module Supporting Three-Wire SPI (all four modes) and I2CTM Master and Slave modes * Addressable USART module: - Supports RS-485 and RS-232 * Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1.2 - Auto-wake-up on Start bit - Auto-Baud Detect * Dual Analog Comparators with Input Multiplexing Power-Managed Modes: * * * * * * * * * Run: CPU On, Peripherals On Idle: CPU Off, Peripherals On Sleep: CPU Off, Peripherals Off Run mode Current Down to 14 A Typical Idle mode Currents Down to 5.8 A Typical Sleep mode Currents Down to 0.1 A Typical Timer1 Oscillator: 1.8 A, 32 kHz, 2V Watchdog Timer: 2.1 A Typical Two-Speed Oscillator Start-up Flexible Oscillator Structure: * Four Crystal modes: - LP: Up to 200 kHz - XT: Up to 4 MHz - HS: Up to 40 MHz - HSPLL: 4-10 MHz (16-40 MHz internal) * 4x Phase Lock Loop (available for crystal and internal oscillators) * Two External RC modes, Up to 4 MHz * Two External Clock modes, Up to 40 MHz * Internal Oscillator Block: - Eight selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User-tunable to compensate for frequency drift * Secondary Oscillator Using Timer1 at 32 kHz * Fail-Safe Clock Monitor: - Allows for safe shutdown of device if primary or secondary clock fails Special Microcontroller Features: * C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code * 1000 Erase/Write Cycle Flash Program Memory Typical * Flash Retention: 100 Years Typical * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 132s - 2% stability over VDD and temperature * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) via Two Pins * Wide Operating Voltage Range: 2.0V to 5.5V Note: This document is supplemented by the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). See Section 1.0 "Device Overview". (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 1 PIC18F6393/6493/8393/8493 Program Memory Device Flash # Single-Word SRAM (bytes) Instructions (bytes) 8K 16K 8K 16K 4096 8192 4096 8192 768 768 768 768 I/O LCD (pixel) 128 128 192 192 12-Bit CCP A/D (PWM) (channels) 12 12 12 12 2 2 2 2 MSSP SPI Y Y Y Y Master I2CTM Y Y Y Y EUSART/ AUSART Data Memory Comparators Timers 8/16-Bit 1/3 1/3 1/3 1/3 PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493 50 50 66 66 1/1 1/1 1/1 1/1 2 2 2 2 Pin Diagrams 64-Pin TQFP RE7/CCP2(1)/SEG31 RE4/COM1 RE5/COM2 RE6/COM3 RD1/SEG1 RD2/SEG2 RD3/SEG3 RD4/SEG4 RD5/SEG5 RD6/SEG6 RD0/SEG0 VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RD7/SEG7 LCDBIAS3 COM0 VSS LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 VSS VDD RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22 RF3/AN8/SEG21 RF2/AN7/C1OUT/SEG20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13 PIC18F6393 PIC18F6493 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RF1/AN6/C2OUT/SEG19 RF0/AN5/SEG18 AVSS RA3/AN3/VREF+/SEG17 RA2/AN2/VREF-/SEG16 RA5/AN4/HLVDIN/SEG15 Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39896A-page 2 Preliminary RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1) RC0/T1OSO/T13CKI RC7/RX1/DT1 RC6/TX1/CK1 RA1/AN1 RA0/AN0 AVDD VDD VSS (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 Pin Diagrams (Continued) 80-Pin TQFP RH1/SEG46 RH0/SEG47 RE7/CCP2(1)/SEG31 RJ0/SEG32 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/SEG45 RH3/SEG44 LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 VSS VDD RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22 RF3/AN8/SEG21 RF2/AN7/C1OUT/SEG20 RH7/SEG43 RH6/SEG42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RJ2/SEG34 RJ3/SEG35 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13 RJ7/SEG36 RJ6/SEG37 PIC18F8393 PIC18F8493 RF1/AN6/C2OUT/SEG19 RF0/AN5/SEG18 RJ4/SEG39 AVSS RA3/AN3/VREF+/SEG17 RA2/AN2/VREF-/SEG16 RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1) RA5/AN4/HLVDIN/SEG15 Note 1: RE7 is the alternate pin for CCP2 multiplexing. (c) 2007 Microchip Technology Inc. Preliminary RC0/T1OSO/T13CKI RC7/RX1/DT1 RC6/TX1/CK1 RH5/SEG41 RH4/SEG40 RJ5/SEG38 RA1/AN1 RA0/AN0 AVDD VSS VDD RJ1/SEG33 RE4/COM1 RE5/COM2 RE6/COM3 RD0/SEG0 RD1/SEG1 RD2/SEG2 RD3/SEG3 RD4/SEG4 RD5/SEG5 RD6/SEG6 RD7/SEG7 LCDBIAS3 COM0 VDD VSS DS39896A-page 3 PIC18F6393/6493/8393/8493 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 29 3.0 Special Features of the CPU ...................................................................................................................................................... 39 4.0 Electrical Characteristics ........................................................................................................................................................... 41 5.0 Packaging Information................................................................................................................................................................ 45 Appendix A: Revision History............................................................................................................................................................... 47 Appendix B: Device Differences........................................................................................................................................................... 47 Appendix C: Conversion Considerations ............................................................................................................................................. 48 Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................ 48 Appendix E: migration from Mid-Range to Enhanced Devices ............................................................................................................ 49 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................... 49 Index .................................................................................................................................................................................................... 51 The Microchip Web Site ....................................................................................................................................................................... 53 Customer Change Notification Service ................................................................................................................................................ 53 Customer Support ................................................................................................................................................................................ 53 Reader Response ................................................................................................................................................................................ 54 Product Identification System............................................................................................................................................................... 55 DS39896A-page 4 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 5 PIC18F6393/6493/8393/8493 NOTES: DS39896A-page 6 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 1.0 DEVICE OVERVIEW 1.2 This document contains device-specific information for the following devices: * PIC18F6393 * PIC18F6493 * PIC18F8393 * PIC18F8493 Details on Individual Family Members Devices in the PIC18F6393/6493/8393/8493 family are available in 64-pin (PIC18F6X93) and 80-pin (PIC18F8X93) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2, respectively. The devices are differentiated from each other in the following ways: * I/O Ports: - 64-pin devices - 7 bidirectional ports - 80-pin devices - 9 bidirectional ports * LCD Pixels: - 64-pin devices - 128 (32 SEGs x 4 COMs) pixels can be driven - 80-pin devices - 192 (48 SEGs x 4 COMs) pixels can be driven * Flash Program Memory: - PIC18FX393 devices - 8 Kbytes - PIC18FX493 devices - 16 Kbytes All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F6393/6493/8393/8493 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an "F" in the part number (such as PIC18F6393), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF6490), function over an extended VDD range of 2.0V to 5.5V. Note: This data sheet documents only the devices' features and specifications that are in addition to the features and specifications of the PIC18F6390/6490/8390/8490 devices. For information on the features and specifications shared by the PIC18F6393/ 6493/8393/8493 and PIC18F6390/6490/ 8390/8490 devices, see the "PIC18F6390/ 6490/8390/8490 Data Sheet" (DS39629). This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price. In addition to these features, the PIC18F6393/6493/8393/8493 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power-sensitive applications. 1.1 Special Features * 12-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduces code overhead. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 7 PIC18F6393/6493/8393/8493 TABLE 1-1: DEVICE FEATURES Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Number of Pixels the LCD Driver Can Drive Timers Capture/Compare/PWM Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) PIC18F6393 DC - 40 MHz 8K 4096 768 22 PIC18F6493 DC - 40 MHz 16K 8192 768 22 PIC18F8393 DC - 40 MHz 8K 4096 768 22 PIC18F8493 DC - 40 MHz 16K 8192 768 22 Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G, H, J F, G, H, J 128 (32 SEGs x 4 COMs) 4 2 128 (32 SEGs x 4 COMs) 4 2 192 (48 SEGs x 4 COMs) 4 2 192 (48 SEGs x 4 COMs) 4 2 MSSP, AUSART, MSSP, AUSART, MSSP, AUSART, MSSP, AUSART, Enhanced USART Enhanced USART Enhanced USART Enhanced USART 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled 64-Pin TQFP Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled 64-Pin TQFP Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled 80-Pin TQFP Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled 80-Pin TQFP Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages DS39896A-page 8 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 FIGURE 1-1: Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH PIC18F6X93 (64-PIN) BLOCK DIAGRAM Data Bus<8> Data Latch Data Memory (3.9 Kbytes) Address Latch 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC PORTB PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 RA3/AN3/VREF+/SEG17 RA4/T0CKI/SEG14 RA5/AN4/HLVDIN/SEG15 OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1 8 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory (48/64 Kbytes) Data Latch 8 STKPTR Table Latch Instruction Bus <16> ROM Latch Address Decode IR 8 PORTD Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 x 8 Multiply 8 W 8 8 ALU<8> 8 PORTF 8 PORTE RD7/SEG7:RD0/SEG0 OSC1(3) OSC2 (3) Internal Oscillator Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor 8 LCDBIAS1 LCDBIAS2 LCDBIAS3 COM0 RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2(1)/SEG31 RF0/AN5/SEG18 RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CVREF/SEG23 RF6/AN11/SEG24 RF7/SS/SEG25 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 MCLR/VPP/RG5(2) T1OSI T1OSO MCLR(2) VDD, VSS Precision Band Gap Reference BOR HLVD ADC 12-Bit PORTG Timer0 Timer1 Timer2 Timer3 Comparators CCP1 CCP2 MSSP EUSART1 AUSART2 LCD Driver Note 1: 2: 3: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RE7 when CCP2MX is not set. RG5 is only available when MCLR functionality is disabled. OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section 2.0 "Oscillator Configurations" of the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 9 PIC18F6393/6493/8393/8493 FIGURE 1-2: Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH PIC18F8X93 (80-PIN) BLOCK DIAGRAM Data Bus<8> Data Latch Data Memory (3.9 Kbytes) Address Latch PORTB 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 RA3/AN3/VREF+/SEG17 RA4/T0CKI/SEG14 RA5/AN4/HLVDIN/SEG15 OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1 8 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory (48/64 Kbytes) Data Latch 8 STKPTR Table Latch Instruction Bus <16> ROM Latch Address Decode PORTD 8 IR RD7/SEG7:RD0/SEG0 Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 x 8 Multiply 8 W 8 8 8 PORTE LCDBIAS1 LCDBIAS2 LCDBIAS3 COM0 RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2(1)/SEG31 RF0/AN5/SEG18 RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CVREF/SEG23 RF6/AN11/SEG24 RF7/SS/SEG25 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 MCLR/VPP/RG5(2) OSC1(3) OSC2 (3) Internal Oscillator Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor 8 ALU<8> 8 PORTF T1OSI T1OSO MCLR(2) VDD, VSS Precision Band Gap Reference PORTG PORTH BOR HLVD ADC 12-Bit Timer0 Timer1 Timer2 Timer3 RH3/SEG47:RH0/SEG44 RH7/SEG40:RH4/SEG43 PORTJ RJ3/SEG35:RJ0/SEG32 Comparators CCP1 CCP2 LCD Driver MSSP EUSART1 AUSART2 RJ7/SEG36:RJ4/SEG39 Note 1: 2: 3: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set and RE7 when CCP2MX is not set. RG5 is only available when MCLR functionality is disabled. OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section 2.0 "Oscillator Configurations" of the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). DS39896A-page 10 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS Pin Number TQFP 7 I P I 39 I I ST Pin Buffer Type Type Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Pin Name MCLR/VPP/RG5 MCLR VPP RG5 OSC1/CLKI/RA7 OSC1 CLKI ST ST RA7 OSC2/CLKO/RA6 OSC2 CLKO 40 I/O O O Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. -- -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. RA6 I/O TTL Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 11 PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/SEG16 RA2 AN2 VREFSEG16 RA3/AN3/VREF+/SEG17 RA3 AN3 VREF+ SEG17 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 RA5/AN4/HLVDIN/SEG15 RA5 AN4 HLVDIN SEG15 RA6 RA7 24 I/O I 23 I/O I 22 I/O I I O 21 I/O I I O 28 I/O I O 27 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 4. Low-Voltage Detect input. SEG15 output for LCD. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. ST/OD ST Analog Digital I/O. Open-drain when configured as output. Timer0 external clock input. SEG14 output for LCD. TTL Analog Analog Analog Digital I/O. Analog input 3. A/D reference voltage (High) input. SEG17 output for LCD. TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (Low) input. SEG16 output for LCD. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 12 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1/SEG8 RB1 INT1 SEG8 RB2/INT2/SEG9 RB2 INT2 SEG9 RB3/INT3/SEG10 RB3 INT3 SEG10 RB4/KBI0/SEG11 RB4 KBI0 SEG11 RB5/KBI1 RB5 KBI1 RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD 48 I/O I 47 I/O I O 46 I/O I O 45 I/O I O 44 I/O I O 43 I/O I 42 I/O I I/O 37 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. TTL TTL Digital I/O. Interrupt-on-change pin. TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG11 output for LCD. TTL ST Analog Digital I/O. External interrupt 3. SEG10 output for LCD. TTL ST Analog Digital I/O. External interrupt 2. SEG9 output for LCD. TTL ST Analog Digital I/O. External interrupt 1. SEG8 output for LCD. TTL ST Digital I/O. External interrupt 0. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 13 PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(1) RC2/CCP1/SEG13 RC2 CCP1 SEG13 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO/SEG12 RC5 SDO SEG12 RC6/TX1/CK1 RC6 TX1 CK1 RC7/RX1/DT1 RC7 RX1 DT1 30 I/O O I 29 I/O I I/O 33 I/O I/O O 34 I/O I/O I/O 35 I/O I I/O 36 I/O O O 31 I/O O I/O 32 I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). ST -- Analog Digital I/O. SPI data out. SEG12 output for LCD. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST ST Analog Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. SEG13 output for LCD. ST CMOS ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 14 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 RD1/SEG1 RD1 SEG1 RD2/SEG2 RD2 SEG2 RD3/SEG3 RD3 SEG3 RD4/SEG4 RD4 SEG4 RD5/SEG5 RD5 SEG5 RD6/SEG6 RD6 SEG6 RD7/SEG7 RD7 SEG7 58 I/O O 55 I/O O 54 I/O O 53 I/O O 52 I/O O 51 I/O O 50 I/O O 49 I/O O ST Analog Digital I/O. SEG7 output for LCD. ST Analog Digital I/O. SEG6 output for LCD. ST Analog Digital I/O. SEG5 output for LCD. ST Analog Digital I/O. SEG4 output for LCD. ST Analog Digital I/O. SEG3 output for LCD. ST Analog Digital I/O. SEG2 output for LCD. ST Analog Digital I/O. SEG1 output for LCD. ST Analog Digital I/O. SEG0 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 15 PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. LCDBIAS1 LCDBIAS1 LCDBIAS2 LCDBIAS2 LCDBIAS3 LCDBIAS3 COM0 COM0 RE4/COM1 RE4 COM1 RE5/COM2 RE5 COM2 RE6/COM3 RE6 COM3 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 2 I 1 I 64 I 63 O 62 I/O O 61 I/O O 60 I/O O 59 I/O I/O O ST ST Analog Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. SEG31 output for LCD. ST Analog Digital I/O. COM3 output for LCD. ST Analog Digital I/O. COM2 output for LCD. ST Analog Digital I/O. COM1 output for LCD. Analog COM0 output for LCD. Analog BIAS3 input for LCD. Analog BIAS2 input for LCD. Analog BIAS1 input for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 16 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF0/AN5/SEG18 RF0 AN5 SEG18 RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21 RF3 AN8 SEG21 RF4/AN9/SEG22 RF4 AN9 SEG22 RF5/AN10/CVREF/SEG23 RF5 AN10 CVREF SEG23 RF6/AN11/SEG24 RF6 AN11 SEG24 RF7/SS/SEG25 RF7 SS SEG25 18 I/O I O 17 I/O I O O 16 I/O I O O 15 I/O I O 14 I/O I O 13 I/O I O O 12 I/O I O 11 I/O I O ST TTL Analog Digital I/O. SPITM slave select input. SEG25 output for LCD. ST Analog Analog Digital I/O. Analog input 11. SEG24 output for LCD. ST Analog Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. SEG23 output for LCD. ST Analog Analog Digital I/O. Analog input 9. SEG22 output for LCD. ST Analog Analog Digital I/O. Analog input 8. SEG21 output for LCD. ST Analog -- Analog Digital I/O. Analog input 7. Comparator 1 output. SEG20 output for LCD. ST Analog -- Analog Digital I/O. Analog input 6. Comparator 2 output. SEG19 output for LCD. ST Analog Analog Digital I/O. Analog input 5. SEG18 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 17 PIC18F6393/6493/8393/8493 TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/SEG30 RG0 SEG30 RG1/TX2/CK2/SEG29 RG1 TX2 CK2 SEG29 RG2/RX2/DT2/SEG28 RG2 RX2 DT2 SEG28 RG3/SEG27 RG3 SEG27 RG4/SEG26 RG4 SEG26 RG5 VSS VDD AVSS AVDD 9, 25, 41, 56 10, 26, 38, 57 20 19 P P P P -- -- -- -- 3 I/O O 4 I/O O I/O O 5 I/O I I/O O 6 I/O O 8 I/O O ST Analog Digital I/O. SEG26 output for LCD. See MCLR/VPP/RG5 pin. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Ground reference for analog modules. Positive supply for analog modules. ST Analog Digital I/O. SEG27 output for LCD. ST ST ST Analog Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). SEG28 output for LCD. ST -- ST Analog Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). SEG29 output for LCD. ST Analog Digital I/O. SEG30 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 18 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS Pin Number TQFP 9 I P I 49 I I ST Pin Buffer Type Type Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Pin Name MCLR/VPP/RG5 MCLR VPP RG5 OSC1/CLKI/RA7 OSC1 CLKI ST ST RA7 OSC2/CLKO/RA6 OSC2 CLKO 50 I/O O O Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. -- -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. RA6 I/O TTL Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 19 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/SEG16 RA2 AN2 VREFSEG16 RA3/AN3/VREF+/SEG17 RA3 AN3 VREF+ SEG17 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 RA5/AN4/HLVDIN/SEG15 RA5 AN4 HLVDIN SEG15 RA6 RA7 30 I/O I 29 I/O I 28 I/O I I O 27 I/O I I O 34 I/O I O 33 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 4. Low-Voltage Detect input. SEG15 output for LCD. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. ST/OD ST Analog Digital I/O. Open-drain when configured as output. Timer0 external clock input. SEG14 output for LCD. TTL Analog Analog Analog Digital I/O. Analog input 3. A/D reference voltage (High) input. SEG17 output for LCD. TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (Low) input. SEG16 output for LCD. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 20 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1/SEG8 RB1 INT1 SEG8 RB2/INT2/SEG9 RB2 INT2 SEG9 RB3/INT3/SEG10 RB3 INT3 SEG10 RB4/KBI0/SEG11 RB4 KBI0 SEG11 RB5/KBI1 RB5 KBI1 RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD 58 I/O I 57 I/O I O 56 I/O I O 55 I/O I O 54 I/O I O 53 I/O I 52 I/O I I/O 47 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. TTL TTL Digital I/O. Interrupt-on-change pin. TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG11 output for LCD. TTL ST Analog Digital I/O. External interrupt 3. SEG10 output for LCD. TTL ST Analog Digital I/O. External interrupt 2. SEG9 output for LCD. TTL ST Analog Digital I/O. External interrupt 1. SEG8 output for LCD. TTL ST Digital I/O. External interrupt 0. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 21 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(1) RC2/CCP1/SEG13 RC2 CCP1 SEG13 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO/SEG12 RC5 SDO SEG12 RC6/TX1/CK1 RC6 TX1 CK1 RC7/RX1/DT1 RC7 RX1 DT1 36 I/O O I 35 I/O I I/O 43 I/O I/O O 44 I/O I/O I/O 45 I/O I I/O 46 I/O O O 37 I/O O I/O 38 I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). ST -- Analog Digital I/O. SPI data out. SEG12 output for LCD. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST ST Analog Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. SEG13 output for LCD. ST CMOS ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 22 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 RD1/SEG1 RD1 SEG1 RD2/SEG2 RD2 SEG2 RD3/SEG3 RD3 SEG3 RD4/SEG4 RD4 SEG4 RD5/SEG5 RD5 SEG5 RD6/SEG6 RD6 SEG6 RD7/SEG7 RD7 SEG7 72 I/O O 69 I/O O 68 I/O O 67 I/O O 66 I/O O 65 I/O O 64 I/O O 63 I/O O ST Analog Digital I/O. SEG7 output for LCD. ST Analog Digital I/O. SEG6 output for LCD. ST Analog Digital I/O. SEG5 output for LCD. ST Analog Digital I/O. SEG4 output for LCD. ST Analog Digital I/O. SEG3 output for LCD. ST Analog Digital I/O. SEG2 output for LCD. ST Analog Digital I/O. SEG1 output for LCD. ST Analog Digital I/O. SEG0 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 23 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. LCDBIAS1 LCDBIAS1 LCDBIAS2 LCDBIAS2 LCDBIAS3 LCDBIAS3 COM0 COM0 RE4/COM1 RE4 COM1 RE5/COM2 RE5 COM2 RE6/COM3 RE6 COM3 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 4 I 3 I 78 I 77 O 76 I/O O 75 I/O O 74 I/O O 73 I/O I/O O ST ST Analog Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. SEG31 output for LCD. ST Analog Digital I/O. COM3 output for LCD. ST Analog Digital I/O. COM2 output for LCD. ST Analog Digital I/O. COM1 output for LCD. Analog COM0 output for LCD. Analog BIAS3 input for LCD. Analog BIAS2 input for LCD. Analog BIAS1 input for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 24 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF0/AN5/SEG18 RF0 AN5 SEG18 RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21 RF3 AN8 SEG21 RF4/AN9/SEG22 RF4 AN9 SEG22 RF5/AN10/CVREF/SEG23 RF5 AN10 CVREF SEG23 RF6/AN11/SEG24 RF6 AN11 SEG24 RF7/SS/SEG25 RF7 SS SEG25 24 I/O I O 23 I/O I O O 18 I/O I O O 17 I/O I O 16 I/O I O 15 I/O I O O 14 I/O I O 13 I/O I O ST TTL Analog Digital I/O. SPI slave select input. SEG25 output for LCD. ST Analog Analog Digital I/O. Analog input 11. SEG24 output for LCD. ST Analog Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. SEG23 output for LCD. ST Analog Analog Digital I/O. Analog input 9. SEG22 output for LCD. ST Analog Analog Digital I/O. Analog input 8. SEG21 output for LCD. ST Analog -- Analog Digital I/O. Analog input 7. Comparator 1 output. SEG20 output for LCD. ST Analog -- Analog Digital I/O. Analog input 6. Comparator 2 output. SEG19 output for LCD. ST Analog Analog Digital I/O. Analog input 5. SEG18 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 25 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/SEG30 RG0 SEG30 RG1/TX2/CK2/SEG29 RG1 TX2 CK2 SEG29 RG2/RX2/DT2/SEG28 RG2 RX2 DT2 SEG28 RG3/SEG27 RG3 SEG27 RG4/SEG26 RG4 SEG26 RG5 5 I/O O 6 I/O O I/O O 7 I/O I I/O O 8 I/O O 10 I/O O ST Analog Digital I/O. SEG26 output for LCD. See MCLR/VPP/RG5 pin. ST Analog Digital I/O. SEG27 output for LCD. ST ST ST Analog Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). SEG28 output for LCD. ST -- ST Analog Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). SEG29 output for LCD. ST Analog Digital I/O. SEG30 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 26 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTH is a bidirectional I/O port. RH0/SEG47 RH0 SEG47 RH1/SEG46 RH1 SEG46 RH2/SEG45 RH2 SEG45 RH3/SEG44 RH3 SEG44 RH4/SEG40 RH4 SEG40 RH5/SEG41 RH5 SEG41 RH6/SEG42 RH6 SEG42 RH7/SEG43 RH7 SEG43 79 I/O O 80 I/O O 1 I/O O 2 I/O O 22 I/O O 21 I/O O 20 I/O O 19 I/O O ST Analog Digital I/O. SEG43 output for LCD. ST Analog Digital I/O. SEG42 output for LCD. ST Analog Digital I/O. SEG41 output for LCD. ST Analog Digital I/O. SEG40 output for LCD. ST Analog Digital I/O. SEG44 output for LCD. ST Analog Digital I/O. SEG45 output for LCD. ST Analog Digital I/O. SEG46 output for LCD. ST Analog Digital I/O. SEG47 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 27 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Buffer Type Type Description PORTJ is a bidirectional I/O port. RJ0/SEG32 RJ0 SEG32 RJ1/SEG33 RJ1 SEG33 RJ2/SEG34 RJ2 SEG34 RJ3/SEG35 RJ3 SEG35 RJ4/SEG39 RJ4 SEG39 RJ5/SEG38 RJ5 SEG38 RJ6/SEG37 RJ6 SEG37 RJ7/SEG36 RJ7 SEG36 VSS VDD AVSS AVDD 62 I/O O 61 I/O O 60 I/O O 59 I/O O 39 I/O O 40 I/O O 41 I/O O 42 I/O O 11, 31, 51, 70 12, 32, 48, 71 26 25 P P P P ST Analog -- -- -- -- Digital I/O. SEG36 output for LCD. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Ground reference for analog modules. Positive supply for analog modules. ST Analog Digital I/O. SEG37 output for LCD. ST Analog Digital I/O SEG38 output for LCD. ST Analog Digital I/O. SEG39 output for LCD. ST Analog Digital I/O. SEG35 output for LCD. ST Analog Digital I/O. SEG34 output for LCD. ST Analog Digital I/O. SEG33 output for LCD. ST Analog Digital I/O. SEG32 output for LCD. Pin Name Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39896A-page 28 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The ADCON0 register, shown in Register 2-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 2-2, configures the functions of the port pins. The ADCON2 register, shown in Register 2-3, configures the A/D clock source, programmed acquisition time and justification. The Analog-to-Digital (A/D) Converter module converts an analog input signal to a 12-bit digital number. The module has 12 inputs for both PIC18F6393/6493 (64-pin) and PIC18F8393/8493 (80-pin) devices. The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) REGISTER 2-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-2 ADCON0: A/D CONTROL REGISTER 0 U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Unimplemented(1) 1101 = Unimplemented(1) 1110 = Unimplemented(1) 1111 = Unimplemented(1) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Performing a conversion on unimplemented channels will return a floating input measurement. bit 1 bit 0 Note 1: REGISTER 2-2: U-0 ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 29 PIC18F6393/6493/8393/8493 REGISTER 2-2: -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADCON1: A/D CONTROL REGISTER 1 (CONTINUED) -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 0 Unimplemented: Read as `0' VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF+ 00 01 10 11 AVDD External VREF+ AVDD External VREF+ A/D VREFAVSS AVSS External VREFExternal VREF- bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits AN10 AN11 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 A A A A A A A A A A A A A A D D PCFG<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AN0 A A A A A A A A A A A A A A A D (c) 2007 Microchip Technology Inc. A A A A D D D D D D D D D D D D A A A A A D D D D D D D D D D D A A A A A A D D D D D D D D D D A A A A A A A D D D D D D D D D A A A A A A A A D D D D D D D D A A A A A A A A A D D D D D D D A A A A A A A A A A D D D D D D A A A A A A A A A A A D D D D D A A A A A A A A A A A A D D D D A A A A A A A A A A A A A D D D A = Analog input D = Digital I/O DS39896A-page 30 Preliminary PIC18F6393/6493/8393/8493 REGISTER 2-3: R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADCON2: A/D CONTROL REGISTER 2 U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. bit 6 bit 5-3 bit 2-0 Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 31 PIC18F6393/6493/8393/8493 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+/SEG17 and RA2/AN2/VREF-/SEG16 pins. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 2-1. FIGURE 2-1: A/D BLOCK DIAGRAM CHS3:CHS0 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 12-Bit A/D Converter (Input Voltage) 0011 0010 VCFG1:VCFG0 AVDD(1) Reference Voltage VREF+ VREFX0 X1 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0001 0000 1X 0X AVSS(1) Note 1: I/O pins have diode protection to VDD and VSS. DS39896A-page 32 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 The value in the ADRESH:ADRESL registers is unknown following Power-on and Brown-out Resets and is not affected by any other Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 2.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to perform an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0<1>) 5. Wait for A/D conversion to complete by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. FIGURE 2-2: FFFh FFEh Digital Code Output A/D TRANSFER FUNCTION 003h 002h 001h 000h 0.5 LSB 1.5 LSB 2.5 LSB 1 LSB 2 LSB 3 LSB 4094.5 LSB 4095.5 LSB 4094 LSB 4095 LSB 2. 3. 4. Analog Input Voltage FIGURE 2-3: ANALOG INPUT MODEL VDD VT = 0.6V RIC 1k Sampling Switch SS RSS Rs ANx VAIN CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Sampling Switch SS = Sample/Hold Capacitance (from DAC) CHOLD RSS = Sampling Switch Resistance 6V 5V VDD 4V 3V 2V 1 2 3 4 Sampling Switch (k) (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 33 PIC18F6393/6493/8393/8493 2.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 2-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 2-1 may be used. This equation assumes that 1/2 LSb error is used (4096 steps for the 12-bit A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Equation 2-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 3V Rss = 4 k 85C (system max.) EQUATION 2-1: TACQ = = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF EQUATION 2-2: VHOLD or TC = = A/D MINIMUM CHARGING TIME (VREF - (VREF/4096)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) - (CHOLD)(RIC + RSS + RS) ln(1/4096) EQUATION 2-3: TACQ TAMP TCOFF = = = 0.2 s CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/4096) s -(25 pF) (1 k + 4 k + 2.5 k) ln(0.0002441) s 1.56 s 0.2 s + 1.56 s + 1.2 s 2.96 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. TC = TACQ = DS39896A-page 34 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 2.2 Selecting and Configuring Acquisition Time 2.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>), which provide a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 13 TAD per 12-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD. (See parameter 130 for more information.) Table 2-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 2-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(1) ADCS2:ADCS0 000 100 001 101 010 110 x11 Assumes TAD Min. = 0.8 s Maximum FOSC 2.50 MHz 5.00 MHz 10.00 MHz 20.00 MHz 40.00 MHz 40.00 MHz 1.00 MHz(2) Note 1: 2: The RC source has a typical TAD time of 2.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC divider should be used instead; otherwise, the A/D accuracy specification may not be met. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 35 PIC18F6393/6493/8393/8493 2.4 Operation in Power-Managed Modes 2.5 Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Analog conversion on pins configured as digital pins can be performed. The voltage on the pin will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used. The ACQT2:ACQT0 bits do not need to be adjusted as the ADCS2:ADCS0 bits adjust the TAD time for the new clock speed. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires the A/D FRC clock to be selected. If the ACQT2:ACQT0 bits are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39896A-page 36 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 2.6 A/D Conversions Figure 2-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 2-5 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT2:ACQT0 bits are set to `010' and a 4 TAD acquisition time has been selected before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will not be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Code should wait at least 2 s after enabling the A/D before beginning an acquisition and conversion cycle. 2.7 Discharge The discharge phase is used to initialize the value of the holding capacitor. The array is discharged before every sample. This feature helps to optimize the unity gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous-measure values. FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Discharge (typically 200 ns) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TAD Cycles 4 1 2 b11 3 b10 4 b9 5 b8 6 b7 7 b6 8 b5 9 b4 10 b3 11 b2 12 b1 13 b0 TAD1 Discharge (typically 200 ns) TACQT Cycles 1 2 3 Automatic Acquisition Time Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 37 PIC18F6393/6493/8393/8493 2.8 Use of the ECCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. TABLE 2-2: Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 TRISA TRISF TRISH(2) REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP -- -- -- Bit 4 INT0IE TX1IF TX1IE TX1IP -- -- -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP HLVDIF HLVDIE HLVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values (3) (3) (3) (3) (3) (3) (3) (3) (3) GIE/GIEH PEIE/GIEL -- -- -- OSCFIF OSCFIE OSCFIP ADIF ADIE ADIP CMIF CMIE CMIP A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM TRISA7(1) TRISF7 TRISH7 -- -- -- TRISA6(1) TRISF6 TRISH6 CHS3 VCFG1 ACQT2 TRISA5 TRISF5 TRISH5 CHS2 VCFG0 ACQT1 TRISA4 TRISF4 TRISH4 CHS1 PCFG3 ACQT0 TRISA3 TRISF3 TRISH3 CHS0 PCFG2 ADCS2 TRISA2 TRISF2 TRISH2 GO/DONE PCFG1 ADCS1 TRISA1 TRISF1 TRISH1 ADON PCFG0 ADCS0 TRISA0 TRISF0 TRISH0 (3) (3) (3) (3) (3) (3) Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2: These registers are not implemented on 64-pin devices. 3: For these Reset values, see the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). DS39896A-page 38 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 3.0 Note: SPECIAL FEATURES OF THE CPU For additional details on the Configuration bits, refer to Section 23.1 "Configuration Bits" in the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). Device ID information presented in this section is for the PIC18F6393/6493/8393/8493 devices only. 3.1 Device ID Registers The Device ID registers are "read-only" registers. They identify the device type and revision to device programmers and can be read by firmware using table reads. PIC18F6393/6493/8393/8493 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These include: * Device ID Registers TABLE 3-1: File Name DEVICE IDs Bit 7 DEV2 DEV10 Bit 6 DEV1 DEV9 Bit 5 DEV0 DEV8 Bit 4 REV4 DEV7 Bit 3 REV3 DEV6 Bit 2 REV2 DEV5 Bit 1 REV1 DEV4 Bit 0 REV0 DEV3 Default/ Unprogrammed Value xxxx xxxx(1) xxxx xxxx(1) 3FFFFEh DEVID1 3FFFFFh DEVID2 Legend: x = unknown Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the user. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 39 PIC18F6393/6493/8393/8493 REGISTER 3-1: R DEV2 bit 7 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 bit 4-0 DEV2:DEV0: Device ID bits See Register 3-2 for a complete listing. REV4:REV0: Revision ID bits These bits are used to indicate the device revision. DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6393/6493/8393/8493 DEVICES R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 REGISTER 3-2: R DEV10 bit 7 Legend: R = Read-only bit DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6393/6493/8393/8493 DEVICES R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0 P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-0 DEV10:DEV3: Device ID bits Device PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493 DEV10:DEV3 (DEVID2<7:0>) 0001 1010 0000 1110 0001 1010 0000 1110 DEV2:DEV0 (DEVID1<7:5>) 000 000 001 001 DS39896A-page 40 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 4.0 ELECTRICAL CHARACTERISTICS Note: Other than some basic data, this section documents only the PIC18F6393/6493/8393/8493 devices' specifications that differ from those of the PIC18F6390/6490/8390/8490 devices. For detailed information on the electrical specifications shared by the PIC18F6393/6493/8393/8493 and PIC18F6390/6490/8390/8490 devices, see the "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RG5 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP/ RG5 pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 41 PIC18F6393/6493/8393/8493 FIGURE 4-1: PIC18F6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FX393/X493 4.2V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V Voltage 40 MHz Frequency FIGURE 4-2: PIC18LF6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFX393/X493 4.2V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V Voltage 4 MHz 40 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC(R) device in the application. DS39896A-page 42 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 TABLE 4-1: Param No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 Sym NR EIL EDL EOFF EGN -- A/D CONVERTER CHARACTERISTICS: PIC18F6393/6493/8393/8493 (INDUSTRIAL) Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity 3 VSS + 3.0V VSS - 0.3V VREFL -- Min -- -- -- -- -- -- -- -- -- Typ -- <1 -- <1 -- <1 -- <1 -- Guaranteed(1) -- -- -- -- -- VDD - VSS VDD + 0.3V VDD - 3.0V VREFH 2.5 Max 12 2.0 2.0 +1.5/-1.0 +1.5/-1.0 5 3 2.00 2.00 Units bit LSB LSB LSB LSB LSB LSB LSB LSB -- V V V V k VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V Conditions VREF 3.0V VREF 3.0V VREF 3.0V VREF 3.0V VREF 3.0V VSS VAIN VREF For 12-bit resolution For 12-bit resolution For 12-bit resolution VREF Reference Voltage Range (VREFH - VREFL) VREFH Reference Voltage High VREFL Reference Voltage Low VAIN ZAIN Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) A50 IREF -- -- -- -- 5 150 A A During VAIN acquisition. During A/D conversion cycle. Note 1: 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from the RA3/AN3/VREF+/SEG17 pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/SEG16 pin or VSS, whichever is selected as the VREFL source. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 43 PIC18F6393/6493/8393/8493 FIGURE 4-3: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) Q4 A/D CLK(1) 132 131 130 A/D DATA 11 10 9 ... ... 3 2 1 0 ADRES ADIF GO OLD_DATA NEW_DATA TCY DONE SAMPLING STOPPED SAMPLE Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 4-2: Param Symbol No. 130 TAD A/D CONVERSION REQUIREMENTS Characteristic A/D Clock Period PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX Min 0.8 1.4 -- -- 13 1.4 -- 0.2 Max 12.5(1) 25.0(1) 1 3 14 -- (Note 4) -- s Units s s s s TAD s Conditions TOSC based, VREF 3.0V VDD = 3.0V; TOSC based, VREF full range A/D RC mode VDD = 3.0V; A/D RC mode 131 132 135 137 TCNV TACQ TSWC TDIS Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time Note 1: 2: 3: 4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. DS39896A-page 44 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 5.0 PACKAGING INFORMATION For packaging information, see the "PIC18F6390/6490/ 8390/8490 Data Sheet" (DS39629). (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 45 PIC18F6393/6493/8393/8493 NOTES: DS39896A-page 46 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (September 2007) Original data sheet for the PIC18F6393/6493/8393/ 8493 devices. DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES PIC18F6393 128 (4 x 32) PIC18F6493 128 (4 x 32) PIC18F8393 192 (4 x 48) PIC18F8493 192 (4 x 48) Features Number of Pixels the LCD Driver Can Drive I/O Ports Flash Program Memory Packages Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G, H, J F, G, H, J 8 Kbytes 64-Pin TQFP 16 Kbytes 64-Pin TQFP 8 Kbytes 80-Pin TQFP 16 Kbytes 80-Pin TQFP (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 47 PIC18F6393/6493/8393/8493 APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available DS39896A-page 48 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442". The changes discussed, while devicespecific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available as Literature Number DS00726. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 49 PIC18F6393/6493/8393/8493 NOTES: DS39896A-page 50 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 INDEX A A/D ...................................................................................... 29 A/D Converter Interrupt, Configuring .......................... 33 Acquisition Requirements ........................................... 34 ADCON0 Register....................................................... 29 ADCON1 Register....................................................... 29 ADCON2 Register....................................................... 29 ADRESH Register................................................. 29, 32 ADRESL Register ....................................................... 29 Analog Port Pins, Configuring..................................... 36 Associated Registers .................................................. 38 Configuring the Module............................................... 33 Conversion Clock (TAD) .............................................. 35 Conversion Requirements .......................................... 44 Conversion Status (GO/DONE Bit) ............................. 32 Conversions ................................................................ 37 Converter Characteristics ........................................... 43 Discharge.................................................................... 37 Operation in Power-Managed Modes ......................... 36 Selecting and Configuring Acquisition Time ............... 35 Special Event Trigger (ECCP2) .................................. 38 Transfer Function........................................................ 33 Use of the ECCP2 Trigger .......................................... 38 Absolute Maximum Ratings ................................................ 41 ADCON0 Register............................................................... 29 GO/DONE Bit.............................................................. 32 ADCON1 Register............................................................... 29 ADCON2 Register............................................................... 29 ADRESH Register............................................................... 29 ADRESL Register ......................................................... 29, 32 Analog-to-Digital Converter. See A/D. E Electrical Characteristics .................................................... 41 A/D Converter............................................................. 43 Absolute Maximum Ratings ........................................ 41 Low-Power Voltage-Frequency Graph ....................... 42 Voltage-Frequency Graph .......................................... 42 Equations A/D Acquisition Time .................................................. 34 A/D Minimum Charging Time ..................................... 34 Calculating the Minimum Required Acquisition Time ................................................. 34 Errata .................................................................................... 5 I Internet Address ................................................................. 53 Interrupt Sources A/D Conversion Complete .......................................... 33 L LCD Driver Features ....................................................................... 1 M Microchip Internet Web Site................................................ 53 Microcontroller Special Features........................................................... 1 Migration from Baseline to Enhanced Devices ................... 48 Migration from High-End to Enhanced Devices.................. 49 Migration from Mid-Range to Enhanced Devices ............... 49 O Oscillator Structure Features ....................................................................... 1 B Block Diagrams A/D .............................................................................. 32 Analog Input Model ..................................................... 33 PIC18F6X93 ................................................................. 9 PIC18F8X93 ............................................................... 10 P Packaging Information.................................................................. 45 Peripheral Highlights............................................................. 1 Pin Diagrams 64-Pin TQFP................................................................. 2 80-Pin TQFP................................................................. 3 Pin Functions AVDD........................................................................... 28 AVDD........................................................................... 18 AVSS ........................................................................... 28 AVSS ........................................................................... 18 COM0 ................................................................... 16, 24 LCDBIAS1 ............................................................ 16, 24 LCDBIAS2 ............................................................ 16, 24 LCDBIAS3 ............................................................ 16, 24 MCLR/VPP/RG5.................................................... 11, 19 OSC1/CLKI/RA7................................................... 11, 19 OSC2/CLKO/RA6 ................................................. 11, 19 RA0/AN0............................................................... 12, 20 RA1/AN1............................................................... 12, 20 RA2/AN2/VREF-/SEG16........................................ 12, 20 RA3/AN3/VREF+/SEG17....................................... 12, 20 RA4/T0CKI/SEG14............................................... 12, 20 C Compare (ECCP2 Module) Special Event Trigger.................................................. 38 Conversion Considerations ................................................. 48 Customer Change Notification Service ............................... 53 Customer Notification Service............................................. 53 Customer Support ............................................................... 53 D Device Differences .............................................................. 47 Device ID Registers ............................................................ 39 Device Overview ................................................................... 7 Details of Individual Devices ......................................... 7 Features (table)............................................................. 8 Special Features ........................................................... 7 Documentation Most Current Versions .................................................. 5 Related Data Sheet....................................................... 7 (c) 2007 Microchip Technology Inc. DS39896A-page 51 PIC18F6393/6493/8393/8493 RA5/AN4/HLVDIN/SEG15 .................................... 12, 20 RB0/INT0 .............................................................. 13, 21 RB1/INT1/SEG8.................................................... 13, 21 RB2/INT2/SEG9.................................................... 13, 21 RB3/INT3/SEG10.................................................. 13, 21 RB4/KBI0/SEG11.................................................. 13, 21 RB5/KBI1 .............................................................. 13, 21 RB6/KBI2/PGC ..................................................... 13, 21 RB7/KBI3/PGD ..................................................... 13, 21 RC0/T1OSO/T13CKI ............................................ 14, 22 RC1/T1OSI/CCP2 ................................................. 14, 22 RC2/CCP1/SEG13................................................ 14, 22 RC3/SCK/SCL ...................................................... 14, 22 RC4/SDI/SDA ....................................................... 14, 22 RC5/SDO/SEG12 ................................................. 14, 22 RC6/TX1/CK1 ....................................................... 14, 22 RC7/RX1/DT1 ....................................................... 14, 22 RD0/SEG0 ............................................................ 15, 23 RD0/SEG1 .................................................................. 15 RD1/SEG1 .................................................................. 23 RD2/SEG2 ............................................................ 15, 23 RD3/SEG3 ............................................................ 15, 23 RD4/SEG4 ............................................................ 15, 23 RD5/SEG5 ............................................................ 15, 23 RD6/SEG6 ............................................................ 15, 23 RD7/SEG7 ............................................................ 15, 23 RE4/COM1............................................................ 16, 24 RE5/COM2............................................................ 16, 24 RE6/COM3............................................................ 16, 24 RE7/CCP2/SEG31 ................................................ 16, 24 RF0/AN5/SEG18................................................... 17, 25 RF1/AN6/C2OUT/SEG19 ..................................... 17, 25 RF2/AN7/C1OUT/SEG20 ..................................... 17, 25 RF3/AN8/SEG21................................................... 17, 25 RF4/AN9/SEG22................................................... 17, 25 RF5/AN10/CVREF/SEG23 ..................................... 17, 25 RF6/AN11/SEG24................................................. 17, 25 RF7/SS/SEG25 ..................................................... 17, 25 RG0/SEG30 .......................................................... 18, 26 RG1/TX2/CK2/SEG29 .......................................... 18, 26 RG2/RX2/DT2/SEG28 .......................................... 18, 26 RG3/SEG27 .......................................................... 18, 26 RG4/SEG26 .......................................................... 18, 26 RG5....................................................................... 18, 26 RH0/SEG47 ................................................................ 27 RH1/SEG46 ................................................................ 27 RH2/SEG45 ................................................................ 27 RH3/SEG44 ................................................................ 27 RH4/SEG40 ................................................................ 27 RH5/SEG41 ................................................................ 27 RH6/SEG42 ................................................................ 27 RH7/SEG43 ................................................................ 27 RJ0/SEG32 ................................................................. 28 RJ1/SEG33 ................................................................. 28 RJ2/SEG34 ................................................................. 28 RJ3/SEG35 ................................................................. 28 RJ4/SEG39 ................................................................. 28 RJ5/SEG38 ................................................................. 28 RJ6/SEG37 ................................................................. 28 RJ7/SEG36 ................................................................. 28 VDD.............................................................................. 28 VDD.............................................................................. 18 VSS.............................................................................. 28 VSS.............................................................................. 18 Pinout I/O Descriptions PIC18F6X93 ............................................................... 11 PIC18F8X93 ............................................................... 19 Power-Managed Modes and A/D Operation ...................................................... 36 Features ....................................................................... 1 Product Identification System ............................................. 55 R Reader Response............................................................... 54 Registers ADCON0 (A/D Control 0)............................................ 29 ADCON1 (A/D Control 1)............................................ 30 ADCON2 (A/D Control 2)............................................ 31 DEVID1 (Device ID 1)................................................. 40 DEVID2 (Device ID 2)................................................. 40 Revision History.................................................................. 47 S Special Features of the CPU .............................................. 39 Device ID Registers .................................................... 39 T Timing Diagrams A/D Conversion........................................................... 44 W WWW Address ................................................................... 53 WWW, On-Line Support ....................................................... 5 DS39896A-page 52 (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 53 PIC18F6393/6493/8393/8493 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39896A FAX: (______) _________ - _________ Device: PIC18F6393/6493/8393/8493 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39896A-page 54 Preliminary (c) 2007 Microchip Technology Inc. PIC18F6393/6493/8393/8493 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) Device(1), (2) PIC18F6393, PIC18F6493, PIC18F8393, PIC18F8493 - VDD range: 4.2V to 5.5V PIC18LF6393, PIC18LF6493, PIC18LF8393, PIC18LF8493 - VDD range: 2.0V to 5.5V I E PT = -40C to +85C = -40C to +125C = (Industrial) (Extended) c) PIC18LF6393-I/PT 301 = Industrial temp., TQFP package, Extended VDD limits, QTP pattern #301. PIC18LF6393-I/PT = Industrial temp., TQFP package, Extended VDD limits. PIC18F6393-E/PT = Extended temp., TQFP package, normal VDD limits. Temperature Range Package Pattern TQFP (Thin Quad Flatpack) Note 1: 2: F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel TQFP packages only. QTP, SQTP, Code or Special Requirements (blank otherwise) (c) 2007 Microchip Technology Inc. Preliminary DS39896A-page 55 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 09/10/07 DS39896A-page 56 Preliminary (c) 2007 Microchip Technology Inc. |
Price & Availability of PIC18F8493
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |